Hot fuzz: Cascade finds dozens of RISC-V chip bugs using random data storm

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Hot fuzz: Cascade finds dozens of RISC-V chip bugs using random data storm
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ETH Zurich boffins say they've devised a better CPU fuzzer to find flaws

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But current CPU fuzzers have limitations that make them less effective. For example, they may not cover the entire instruction set architecture or they may not manageFlavien Solt and Katharina Ceesay-Seitz, doctoral students at ETH Zurich, and Kaveh Razavi, assistant professor at ETH Zurich, call the project

Unlike other CPU fuzzers, Cascade can construct long random programs that manage the control flow during execution. This allows the fuzzer to more thoroughly probe the silicon. The technique is described inLatest SiFive RISC-V cores aim to boost performance, accelerate AI workloads"The basic idea is to use the ISA simulator to figure out how to entangle the randomized control flow with the randomized data flow," explained Razavi.

Razavi explained that Cascade initially generates an intermediate program in which the control flow is independent of the data stream, but includes placeholders to add this dependency later.

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